Global planarization of multiple layers

ABSTRACT

A method is disclosed for performing global planarization of the top layer of a structure having multiple patterned layers, during fabrication of an integrated circuit (10). An integrated circuit fabricated using the method is also disclosed. The method involves globally planarizing an integrated circuit (10) having a plurality of patterned layers (14, 18) interleaved with a plurality of unpatterned layers (16, 20). Each of the patterned layers (14, 18) is associated with a pattern mask (22, 24). The topmost layer (20) can be an unpatterned layer. Next, the pattern masks (22, 24) are combined to form a planarizing block mask (44) by merging a weighted inverse spatial interpolation of each pattern mask (22, 24). A planarizing block layer (60) is then formed on top of the topmost layer (20) using the planarizing block mask (44). Next, an unpatterned planarizing film layer (62) is formed on top of the planarizing block layer (60). Finally, the film layer (62), the block layer (60) and the topmost layer (20) are etched to cause global planarization of the topmost layer (20).

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to integrated circuit fabrication, andmore particularly, to a method for achieving global planarization of thetop layer of a multiple layer nonplanar structure during fabrication ofintegrated circuits.

BACKGROUND OF THE INVENTION

As device dimensions in integrated circuits continue to decrease,planarization of topographical features becomes more critical. Whenexposing a pattern using photolithography, large differences in stepheight across the exposed area will cause some of the pattern to be outof focus. This effect results from the limited depth of focus availablewith existing photolithography technology. The problem is most seriousfor devices smaller than 1 micron. Existing technology normally canmaintain a good depth of focus between plus or minus 0.3 microns. Whenportions of the exposed areas are out of focus, metal leads may be openor the "via holes" may not open up uniformly.

For submicron-sized devices, therefore, it is desirable to planarizetopographical features before fabricating a subsequent patterned layer.Engineers have proposed two principle methods for achieving globalplanarization: chem-mechanical polishing and patterned resist etchback.In chem-mechanical polishing, a slurry film etches a wafer while a padis used to apply mechanical pressure and increase the etch rate. Areason the wafer that are "higher" on the surface are etched more quickly.Unfortunately, chem-mechanical polishing does not give ideal globalplanarization. Instead, this process causes pattern density effectswhich are more significant as die sizes increase.

Patterned resist etchback involves globally planarizing a structureafter a patterned layer has been formed and an oxide or dielectric layerhas been deposited on top of the patterned level. The oxide layer tendsto be raised in the vicinity of structures on the patterned layer andtends to have valleys where there is no structure on the patternedlayer. The patterned resist etchback process planarizes the oxide level.

The first step in the patterned resist etchback process is to deposit areverse pattern of the patterned layer on top of the oxide. This layer,known as the planarizing block layer, can be formed using a negative ofthe mask used to form the patterned layer. After the reverse pattern hasbeen deposited, the resulting layer comprises structures that fill thevalleys of the oxide layer. Next, a layer of photoresist is spun on,thus providing a substantially planarized surface. The substantiallyplanarized surface is then etched using a process that will etch thephotoresist and oxide at the same rate, thus producing a planarizedoxide surface. After the oxide has been planarized, additional patternedlayers may be deposited on top of the oxide layer.

Although patterned resist etchback is a good method to achieve globalplanarization, it adds a significant number of processing steps as onemust perform the method after forming each patterned level. Theseadditional processing steps also increase the amount of chemicals neededto fabricate an integrated circuit. As a result, patterned resistetchback causes both the cost and time of production to increase.

SUMMARY OF THE INVENTION

The present invention avoids the need to perform patterned resistetchback after fabricating each patterned layer. One aspect of theinvention is a method for performing global planarization of the toplayer of a nonplanar structure having multiple patterned layers usingpatterned resist etchback techniques. First, a plurality of patternedlayers are formed and are interleaved with a plurality of unpatternedlayers. The patterned layers are formed using a mask and the topmostlayer will normally be an unpatterned layer. The pattern masks used informing the patterned layers are then combined to form a planarizingblock mask. The pattern masks are combined by merging a weighted inversespatial interpolation of each pattern mask. Next, a planarizing blocklayer is formed on top of the topmost layer using this planarizing blockmask. An unpatterned planarizing film layer is then formed on top of theplanarizing block layer. The film layer, the block layer, and thetopmost unpatterned layer are then etched to cause planarization of thetopmost unpatterned layer. The detailed description of the inventiondiscloses several variations of the invention.

An important technical advantage of the present invention is that globalplanarization can be performed on the top layer of a nonplanar structurehaving multiple patterned layers using patterned resist etchbacktechniques. Because multiple layers can be planarized simultaneously,patterned resist etchback need not be performed after fabricating eachpatterned layer. Another technical advantage of the invention,therefore, is that the invention saves processing steps. Because theinvention saves processing steps, it also saves processing time andreduces the cost of fabricating integrated circuits. Becauseplanarization need not be performed after fabricating each patternedlayer, the invention also decreases the amount of chemicals required tofabricate a device.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and theadvantages thereof, reference is now made to the following descriptionstaken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a portion of an integrated circuit having a pluralityof patterned layers formed thereon;

FIGS. 2A-2B illustrate a top view of the masks used to form thepatterned layers in the integrated circuit illustrated in FIG. 1;

FIGS. 3A-3B illustrate the inverse of the masks of FIGS. 2A-2B,respectively;

FIGS. 4A-4C illustrate several template masks used with the presentinvention;

FIGS. 5A-5B illustrate a weighted spatial interpolation of the masksillustrated in FIGS. 3A-3B and formed using the template masks of FIGS.4A-4C;

FIG. 6 illustrates a planarizing block mask made in accordance with theteachings of the present invention using the weighted spatialinterpolations illustrated in FIGS. 5A-5B;

FIGS. 7A-7B illustrate alternative template masks that could be usedwith the present invention;

FIGS. 8A-8B illustrate a weighted spatial interpolation of the masksillustrated in FIGS. 2A-2B using the template masks of FIGS. 4A-4C;

FIG. 9 illustrates an intermediate mask formed by summing the weightedspatial interpolations illustrated in FIGS. 8A-8B;

FIGS. 10A-10B illustrate the inverse of the weighted spatialinterpolations illustrated in FIGS. 8A-8B;

FIG. 11 illustrates the integrated circuit of FIG. 1 after a planarizingblock layer has been formed on top of the topmost unpatterned layerutilizing the planarizing block mask illustrated in FIG. 6;

FIG. 12 illustrates the structure of FIG. 11 with an unpatternedplanarizing film layer formed on top of the planarizing block layer andthe unpatterned layer;

FIG. 13 illustrates the structure of FIG. 12 after it has been etched tocause global planarization;

FIG. 14 illustrates an integrated circuit made in accordance with theteachings of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The preferred embodiment of the present invention and its advantages arebest understood by referring to FIGS. 1-14 of the drawings, likenumerals being used for like and corresponding parts of the variousdrawings.

FIG. 1 illustrates a partially completed cross section of an integratedcircuit 10. Integrated circuit 10 comprises substrate 12, firstpatterned layer 14, first unpatterned layer 16, second patterned layer18 and second unpatterned layer 20. First patterned layer 14 is formedon substrate 12 using a mask (not shown). First patterned layer 14, forexample, can be a metal layer.

First unpatterned layer 16 is formed on top of first patterned layer 14.First unpatterned layer 16 can, for example, be an oxide or dielectriclayer. Similarly, second patterned layer 18 can be formed on top offirst unpatterned layer 16 and second unpatterned layer 20 on top ofsecond patterned layer 18. Second patterned layer 18 could also, forexample, be a metal layer, while second unpatterned layer 20 could be anoxide or dielectric layer. To accurately fabricate additional patternedlayers, a designer may desire to globally planarize second unpatternedlayer 20.

The present invention allows a designer to globally planarize the toplayer of a nonplanar structure having multiple patterned layers.Integrated circuit 10 has a plurality of patterned layers interleavedwith a plurality of unpatterned layers, Integrated circuit 10 has twopatterned layers, but the present invention can easily be extended toplanarize structures having more than two patterned layers formedbetween planarizing steps. The topmost layer is normally an unpatternedlayer.

In accordance with the teachings of the present invention, the topmostlayer is planarized using a new type of patterned resist etchbacktechnique. Because the top layer of a structure having multiplepatterned layers is being planarized, the inverse of the mask used toform the patterned layers may not be used directly to form theplanarizing block layer as with existing photoresist etchbacktechniques. Instead, a new planarizing block mask should be createdusing information from each of the masks used to form the patternedlayers.

The discussion below describes a method for achieving planarization ofmultiple patterned layers using a planarizing block mask. There areseveral different ways to make the planarizing block mask in practicingthe invention. The discussion accompanying FIGS. 2a, 2b through 6describes one method of making the mask. The discussion accompanyingFIGS. 8a, 8b and 9 illustrates an alternative method of making the mask,while the discussion of FIG. 10 illustrates yet another alternative formaking the mask. Other equivalent methods of making the mask can bereadily imagined without departing from the scope of the presentinvention. After describing ways of making the blocking mask, FIGS.11-13 illustrate an application of the method to integrated circuit 10.FIG. 14 illustrates an integrated circuit made in accordance with theteachings of the present invention.

The planarizing block mask used to form the planarized block layer maybe formed by combining the pattern masks that were used to form thepatterned layers comprising the structure to be planarized. These masksmay be combined by merging a weighted inverse spatial interpolation ofeach pattern mask.

FIG. 2a illustrates a top view of first pattern mask 22 and FIG. 2billustrates a top view of second pattern mask 24. Each illustrated maskis a portion of a complete mask used to form the patterned layers ofintegrated circuit 10. One section of first pattern mask 22 was used toform first patterned layer 14 of integrated circuit 10 while secondpattern mask 24 was used to form second patterned layer 18 in integratedcircuit 10. Arrows 26 indicate the portion of first pattern mask 22 andsecond pattern mask 24 used to form the vertical slice of integratedcircuit 10 that is illustrated in FIG. 1.

The shaded areas in first pattern mask 22 and second pattern mask 24represent areas where material will be deposited when first patternedlayer 14 and second patterned layer 18 are formed. The clear regions ofthe masks represent areas where no material is created when formingfirst patterned layer 14 and second pattern layer 18. The illustratedmasks may be used with a positive photoresist. Alternatively, an inverseof first pattern mask 22 and second pattern mask 24 could be used with anegative photoresist. In an inverse mask, the shaded areas of firstpattern mask 22 and second pattern mask 24 would become clear while theclear areas would become shaded. The present invention can be used witheither positive or negative photoresist.

First pattern mask 22 and second pattern mask 24 will normally becreated on a computer and be represented by a series of boolean valuescorresponding to specific points on the mask. A shaded area is normallyrepresented as a boolean TRUE while a clear area is normally representedby a boolean FALSE. These representations, however, could easily beinterchanged.

The first step of the first method for making the planarizing block maskis to create inverses of each pattern mask. FIG. 3a illustrates firstinverse mask 26 and FIG. 3b illustrates second inverse mask 28. Firstinverse mask 26 is an inverse of first pattern mask 22 while secondinverse mask 28 is an inverse of second pattern mask 24. As described,an inverse mask can be formed by reversing the shaded portions and theclear portions. Where masks are stored on a computer, all boolean truevalues may be changed to false and all boolean false values may bechanged to true. As an alternative to using first inverse mask 26 andsecond inverse mask 28, first pattern mask 22 and second pattern mask 24could be utilized as inverse masks by using photoresist of an oppositepolarity.

The step of taking an inverse may thus consist of reversing the shadedareas and the clear areas. Otherwise, an inverse mask could be createdby using the pattern mask, and using photoresist when forming theplanarizing block with a polarity opposite to that used to form thepatterned layers. Taking the inverse of the pattern masks to forminverse masks, therefore, encompasses both (1) actually taking theinverse of the pattern masks as described above or (2) leaving thepattern masks unchanged and using the opposite polarity of photoresistwhen forming the planarizing block layer.

Another step in the first method for forming a planarizing block mask isforming template masks. FIG. 4a illustrates first template mask 30 andFIG. 4b illustrates second template mask 32. Each template maskcorresponds to a specific patterned layer. A template mask may becreated for each patterned layer. The template for a particular layer isused to create a weighted spatial interpolation of the pattern mask orinverse mask for that layer. In the first method for making theplanarizing block mask, the template masks can be used to form aweighted spatial interpolation of the inverse masks.

Patterned resist etchback for a structure with single patterned layer,involves forming a planarizing block only in locations where nostructure has been formed on the patterned layer. In the presentinvention, however, it should be considered whether material has beenformed on a multiplicity of patterned layers. To achieve planarization,the size of the planarizing blocks can be varied depending upon thenumber of patterned layers underlying a specific vertical slice of theplanarizing block layer. Forming a planarizing block mask is thus morecomplex when globally planarizing a structure have multiple patternedlayers than when globally planarizing a structure having a singlepatterned layer.

Integrated circuit 10 illustrated in FIG. 1, provides an example of thisphenomena. First patterned layer 14 has approximately the same thicknessas second patterned layer 18. Given this configuration, fourpossibilities exist. First, there can be vertical slices of integratedcircuit 10 where no structure has been formed in either first patternedlayer 14 or second patterned layer 18. In these vertical slices, aplanarizing block should cover the entire vertical slice.

Second, there can be vertical slices of integrated circuit 10 wherestructure appears both on first patterned layer 14 and on secondpatterned layer 18. In this situation, no planarizing block should beformed in this vertical slice as these will be the highest areas oftopography.

Third, there can be vertical slices of integrated circuit 10 wherestructure has been formed on first patterned layer 14 but not on secondpatterned layer 18. In this case, a planarizing block should cover onehalf of the surface area of the vertical slice. By covering only onehalf of the surface area, this planarizing block will lead to betterlocal planarization around this vertical slice.

Fourth, there can be vertical slices of integrated circuit 10 wherestructure has been formed on second patterned layer 18 but not on firstpatterned layer 14. As was the case for the third possibility, aplanarizing block having half of the surface area of the vertical sliceshould be formed for this vertical slice.

This method of forming a planarizing block layer can be extended to forma planarizing block layer for more than two patterned layers and/or forlayers of different thicknesses. Where more than two layers are present,the surface area of the planarizing block should be sized according tothe number of patterned layers in the vertical slice on which structurehas been formed. For example, in an integrated circuit with threepatterned layers, the planarizing block mask could have a surface areaof 0/3, 1/3, 2/3 or 3/3 of the surface area of the vertical slicedepending upon whether structure appears on 3, 2, 1, or 0 patternedlayers respectively.

For integrated circuits where the thickness of the patterned layersvaries, the surface area of the planarizing block may be varieddepending upon the thickness of the patterned structures underlying thevertical slice. The method involves varying the surface area of theplanarizing block in proportion to the thickness of the particular layerunderlying the vertical slice. This method is more fully described belowin connection with FIG. 7.

To vary the area of the planarizing blocks, the planarizing block maskmay be formed by combining a weighted spatial interpolation of theinverse masks of each patterned layer. Taking a weighted spatialinterpolation of the inverse masks involves sampling each mask atspecific locations and combining the samples to form the planarizingblock mask. To form the weighted spatial interpolation of the inversemask, template masks are `multiplied` by the inverse masks. Here, theterm `multiplying` refers to taking the logical AND between the templatemask and the corresponding inverse mask for a specific patterned layer.

The general procedure for forming a template mask is first described ingeneral terms. After this method has been described, a specific exampleis provided by referring to FIGS. 4a-4c. To create the template masks, aglobal template mask can be created that comprises a grid of similarlyshaped units. Each unit may then be subdivided into a plurality ofsubunits. Each unit has at least one subunit associated with eachpatterned layer that is being planarized.

For example, where two patterned layers are being planarized, at leastone subunit in each unit may be associated with each of the twopatterned layers. In addition, each subunit is normally associated withone and only one patterned layer. For the example where two patternedlayers are being planarized, at least two subunits may be used where onesubunit may be associated with one layer and the other subunit may beassociated with the other patterned layer. The area of the subunits maybe weighted based upon the thickness of the patterned layers.

After the global template mask has been designed, a layer template maskassociated with each patterned layer is created. The layer template maskfor a specific layer may comprise a series of boolean values associatedwith each subunit of the global template mask. All boolean values in alayer template mask for a specific layer have a value of false exceptfor the boolean values associated with the subunits that were associatedwith that specific patterned layer when creating the global templatemask.

As an example, when creating layer template masks in attempting toplanarize two patterned layers, a first layer template mask associatedwith the first patterned layer is formed and a second layer templatemask associated with a second patterned layer is formed. The globaltemplate mask may be divided into at least two subunits where onesubunit may be associated with the first patterned layer and one subunitmay be associated with the second patterned layer. All boolean values inthe first template mask are normally set to false except for thoseboolean values for those subunits that were associated with the firstpatterned layer. Similarly, all boolean values are normally set to falsein the second layer template mask except for those boolean values forthose subunits that were associated with the second patterned layer whencreating the global template mask.

The method of creating the layer template masks is more easilyunderstood by referring to FIGS. 4a-4c. As discussed above, FIG. 4aillustrates first layer template mask 30 and FIG. 4b illustrates secondtemplate mask 32. In addition, FIG. 4c illustrates global template mask34. Global template mask 34 has been divided into a grid of similarlyshaped units 36. Global template mask 34 has four columns of eight units36 in each column. Each unit 36 has been divided into two subunits 38.More than two subunits could be used without departing from the scope ofthe present invention as long as each subunit is assigned to one andonly one patterned layer and at least one subunit in each unit isassigned to each patterned layer. In global template mask 34, thosesubunits delineated with the label 1 have been assigned to a firstpatterned layer while those units labeled with the label 2 have beenassigned to a second patterned layer. For the subunits 28 that have thelabels 38 in their interior, the leftmost subunit is assigned to thefirst patterned layer while the rightmost subunit is assigned to thesecond patterned layer.

First layer template mask 30 can be formed according to the methoddescribed above. Given global template mask 34, the subunits 38 of firstlayer template mask 30 have all been assigned a boolean value of FALSE,except for the boolean values associated with those subunits that wereassociated with the first patterned layer in global template mask 34. Infirst layer template mask 30 illustrated in FIG. 4a, a boolean value ofTRUE is indicated by a shaded subunit while a boolean value of FALSE isindicated by an unshaded subunit.

Similarly, second layer template mask 32 can be created by setting allboolean values associated with each subunit of global template mask 34to FALSE except for those subunits that were associated with the secondpatterned layer when creating global template mask 34.

Thus, a layer template mask is associated with each patterned layer. Inthe first method of making the planarizing block mask, a weightedspatial interpolation of each inverse mask is created. A weightedspatial interpolation for a specific patterned layer may be created bytaking the logical AND between the inverse mask and the layer templatemask associated with the particular patterned layer. For example, tocreate the weighted spatial interpolation for the first layer, thelogical AND may be taken between the inverse mask for the firstpatterned layer and the layer template mask for the first patternedlayer.

FIG. 5a illustrates first weighted spatial interpolation 40 and FIG. 5billustrates second weighted spatial interpolation 42. First weightedspatial interpolation 40 was created by multiplying first inverse mask26 by first template mask 30. In other words, first weighted spatialinterpolation 40 was created by multiplying the inverse mask associatedwith the first patterned layer by the layer template mask associatedwith the first patterned layer. First inverse mask 26 can be representedby a series of boolean values each associated with a subunit of globaltemplate mask 34. Again, the term `multiplying` refers to taking thelogical AND between the two masks.

Similarly, second weighted spatial interpolation 42 was created bymultiplying second inverse mask 28 by second layer template mask 32. Theshaded areas in first weighted spatial interpolation 40 and secondweighted spatial interpolation 42 represent areas with a boolean valueof TRUE while the unshaded areas represent a boolean value of FALSE.

First weighted spatial interpolation 40 and second weighted spatialinterpolation 42 may also be referred to as weighted inverse spatialinterpolations of the first and second pattern masks, respectively. Thisterm refers to the fact that first weighted spatial interpolation 40 andsecond weighted spatial interpolation 42 represent weighted spatialinterpolations of the inverse of first pattern mask 22 and secondpattern mask 24.

The final step of the first method for creating the planarizing blockmask involves summing the weighted spatial interpolations of eachpattern mask. Here, summing refers to taking the logical OR between theweighted spatial interpolations. In the general case, the weightedinverse spatial interpolations are summed to form the planarizing blockmask.

For example, FIG. 6 illustrates patterned block mask 44 created usingfirst weighted spatial interpolation 40 and second weighted spatialinterpolation 42. To form patterned block mask 44, first weightedspatial interpolation 40 may be summed with second weighted spatialinterpolation 42. In other words, the weighted spatial interpolation ofthe inverse masks associated with each pattern level may be summed. Thisprocess is also known as merging a weighted inverse spatialinterpolation of each pattern mask. Arrows 46 delineate the slice ofpattern block mask 44 used to form the pattern block layer forintegrated circuit 10 as illustrated in FIG. 11. FIG. 11 is more fullydescribed below.

For the template masks illustrated in FIGS. 4a-4b, the above discussionassumes that the first patterned layer has approximately the samethickness as the second patterned layer. The template masks can beformed differently when the patterned layers have different thicknesses.In a general case, where the patterned layers have differentthicknesses, the subunits can be designed to have an area proportionalto the area of the unit such that the ratio of the area of a particularsubunit to the area of the unit is approximately equal to the ratio ofthe thickness of the patterned layer with which the particular subunitis associated to the sum of the thicknesses for the plurality ofpatterned layers that are being globally planarized.

For example, in planarizing two layers where the first layer has athickness of three times the thickness of the second layer, the area ofthe subunit associated with the first sublayer could be three times aslarge as the area of the subunit associated with the second layer.

FIG. 7a illustrates an example of a first template mask 46 and FIG. 7billustrates a second template mask 48 for patterned layers of differentthicknesses. This example assumes that one is attempting to planarizetwo patterned layers where the first patterned layer has a thicknessapproximately three times as large as the thickness of the secondpatterned layer. As illustrated, the units associated with the firstpatterned layer have a boolean value of TRUE in first template mask 46have been shaded, while those boolean values not associated with thefirst patterned layer in first template mask 46 remain unshaded.Similarly, those subunits associated with the second patterned layerhave been a boolean value of TRUE in second template mask 46 while thosesubunits not associated with the second patterned layer have been set toa boolean value of FALSE and remain unshaded. As illustrated in FIGS. 7aand 7b, those subunits associated with the first patterned layer consumeapproximately 3/4 of the area of a unit while those subunits associatedwith the second patterned layer occupy only approximately 1/4 of thesurface of a unit.

Where the patterned layers have equal thickness, the subunits will haveequal area in the template mask. This method of making a template maskcan be extended to situations involving planarization of more than twolevels. For example, in planarizing three layers simultaneously, wherethe first and second layer have equal thickness and the third layer istwice as thick as the first and second layer, the template mask willhave subunits covering 1/4 of the surface area of a unit for the firstand second layer and subunits covering 1/2 of the area of a unit for thethird layer.

The second method of making the planarizing block mask involves summinga weighted spatial interpolation of each pattern mask to form anintermediate mask. Next, the inverse of the intermediate mask may betaken to form the planarizing block mask.

As above, taking the inverse of the intermediate mask normally involveschanging boolean TRUE values to FALSE and boolean FALSE values to TRUE.Physically, this has the effect of changing shaded areas on the mask tounshaded areas and unshaded areas on the mask to shaded areas.Alternatively, the inverse of the intermediate mask can be taken to formthe planarizing block mask simply by leaving the intermediate maskunchanged and using a polarity of photoresist to form the planarizingblock layer opposite to that of the photoresist used to form thepatterned layers. These two methods are equivalent.

For example, the second method of forming a planarizing block mask canbe illustrated using first pattern mask 22 and second pattern mask 24 ofFIGS. 2a-2b. First a weighted spatial interpolation of each pattern maskis formed. To create the weighted spatial interpolation of each patternmask, a global template mask and a layer template mask for each layermay be created, as described above. Accordingly, first layer templatemask 30 and second layer template mask 32 could be used. Next, aweighted spatial interpolation of each pattern mask may be created bymultiplying the pattern mask for a particular layer by the layertemplate mask associated with that layer.

FIG. 8a illustrates first weighted spatial interpolation 50 and FIG. 8billustrates second weighted spatial interpolation 52 using this method.First weighted spatial interpolation 50 may be formed by multiplyingfirst layer template mask 30 by first pattern mask 22. Second weightedspatial interpolation 52 may be formed by multiplying second layertemplate mask 32 by second pattern mask 24. Again, the step ofmultiplying two masks comprises taking the logical AND of the two masks.

The next step in the second method for creating a planarizing block maskis to sum the weighted spatial interpolations to form an intermediatemask. Again, summing comprises taking the logical OR between theweighted spatial interpolations.

FIG. 9 illustrates an intermediate mask 54 formed in accordance with thesecond method of creating a planarizing block mask. Intermediate mask 54has been formed by summing first weighted spatial interpolation 50 andsecond weighted spatial interpolation 52.

The final step in forming a planarizing block mask in accordance withthe second method is to take the inverse of the intermediate mask toform the planarizing block mask. If a polarity of photoresist is usedthat is opposite to the polarity of the photoresist used to form thepatterned layers, the intermediate mask can be used as the inverse. Inother words, the intermediate mask becomes the planarizing block mask.If photoresist with the same polarity is used as that used to form thepatterned layers, the planarizing block mask may be formed by taking theboolean inverse of the intermediate mask. Either method is equivalent.Referring again to FIG. 9, taking the inverse of intermediate mask 54results in pattern block mask 44 of FIG. 6.

The third method of forming a planarizing block mask involves creating aweighted spatial interpolation of each pattern mask. The inverse of eachof the weighted spatial interpolations is then taken to form inverseinterpolation masks. Finally, the planarizing block mask may be formedby multiplying the inverse interpolation masks.

Applying this method of making a planarizing block mask to first patternmask 22 and second pattern mask 24 of FIGS. 2a-2b, a weighted spatialinterpolation of each pattern mask is first created. The first weightedspatial interpolation 50 of first pattern mask 22 is illustrated in FIG.8a, while FIG. 8b illustrates second weighted spatial interpolation 52of second pattern mask 24. Next, the inverse of these weighted spatialinterpolations may be taken to form inverse interpolation masks. FIG.10a illustrates first inverse interpolation mask 56 and FIG. 10billustrates second inverse interpolation mask 58. First inverseinterpolation mask 56 may be formed by taking the inverse of firstweighted spatial interpolation 52 while second inverse interpolationmask 58 may be formed by taking the inverse of second weighted spatialinterpolation 52.

Finally, the planarizing block mask may be formed by multiplying theinverse interpolation masks. For example, planarizing block mask 44 ofFIG. 6 can be formed by multiplying first inverse interpolation mask 56by second inverse interpolation mask 58.

Due to problems aligning the masks for various layers, the planarizingblock structures in the planarizing block layer will normally be madeslightly smaller than they otherwise would be. The size of the shaded,or TRUE areas of the planarizing block mask can be adjusted or the sizeof the original pattern masks can be adjusted. For example, in the firstmethod discussed above, the positive areas on each of the pattern maskscould be enlarged to form enlarged masks and then the inverse of theenlarged masks could be taken to form inverse masks. The positive areasare the shaded areas in the pattern masks for each layer. By enlargingthese areas, the size of the pattern block areas shrink when the inverseof the enlarged mask is taken.

After a planarizing blocking mask has been formed using any of the abovemethods or their equivalents, a planarizing block layer may be formed ontop of the topmost layer of the integrated circuit. As noted above, thetopmost layer is normally an unpatterned layer. FIG. 11 illustratesplanarizing block layer 60 formed on top of the topmost layer, which issecond unpatterned layer 20. The topmost unpatterned layer is normallythicker than the sum of the thicknesses of the patterned layers. Thethickness of planarizing block layer 60 is normally approximately thesame as the sum of the thicknesses of the patterned layers in thestructure that is being planarized.

In the example illustrated in FIG. 11, patterned layer 60 isapproximately the same thickness as the sum of the thicknesses of firstpatterned layer 14 and second patterned layer 18. Thicker photoresistcould be used if desired. If thicker photoresist is used, the area ofeach planarizing block could be reduced proportionally to the increasein thickness of the photoresist. The desired thickness of thephotoresist depends upon the minimum surface area of a planarizing blockand can be determined empirically for different applications. The sizeof each unit on the template mask will also depend upon the application.If the unit size is too small, there may be problems adding theplanarizing layer of photoresist.

FIG. 11 illustrates planarizing block layer 60 formed on top of thetopmost layer using the planarizing block mask. The slice of integratedcircuit 10 illustrated in FIG. 11 was formed using the slice of firstpattern mask 22 and second pattern mask 24 denoted by the arrows 25 inFIGS. 2a-2b. The portion of planarizing block mask 44 used to form thevertical slice of planarizing block layer 60 illustrated in FIG. 11indicated by arrows 45 in FIG. 6.

After the planarizing block layer has been formed on top of the topmostlayer, an unpatterned planarizing film layer can be formed on top of theplanarizing block layer. FIG. 12 illustrates unpatterned planarizingfilm layer 62 formed on top of planarizing block layer 60. Planarizingblock layer 60 normally comprises photoresist and unpatternedplanarizing film layer 62 also comprises a spun-on layer of photoresist.Unpatterned planarizing film layer 62 is substantially planar, bothlocally and globally.

The final step in globally planarizing the structure having multiplepatterned layers is etching the film layer, block layer and topmostlayer to cause planarization of the topmost layer. As illustrated inFIG. 13, the film layer, the planarizing block layer and the topmostlayer, which is unpatterned layer 20, have been etched such that theunpatterned planarizing film layer 62 and planarizing block layer 60have disappeared. Portions of these layers could, however, remainwithout departing from the scope or the teachings of the presentinvention. The result of this etching step is that unpatterned layer 20is now substantially planar both locally and globally.

FIG. 14 thus illustrates a portion of an integrated circuit 10comprising a substrate 12 and a plurality of patterned layers formed onthe substrate using a pattern mask associated with each of the patternedlayers. A plurality of unpatterned layers is interleaved between thepatterned layers including a second unpatterned layer 20 on top of atleast two patterned layers and at least one additional unpatterned layerwherein the second unpatterned layer 20 has been globally planarized.This layer was planarized by combining the pattern masks to form aplanarizing block mask, forming a planarizing block layer on top of thefirst unpatterned layer using the planarizing block mask, forming anunpatterned planarizing film layer on top of the planarizing blocklayer, and etching the film layer, block layer and second unpatternedlayer 20 at a similar rate. In addition, the integrated circuit willhave at least one additional layer 64 formed on top of the secondunpatterned layer 20.

Although the present invention and its advantages have been described indetail, it should be understood that various changes, substitutions andalterations can be made therein without departing from the spirit andscope of the invention as defined by the appended claims.

What is claimed is:
 1. A method for performing global planarization ofthe top layer of a structure having multiple patterned layers, duringfabrication of an integrated circuit having a plurality of patternedlayers interleaved with a plurality of unpatterned layers wherein eachof said patterned layers is associated with a pattern mask and whereinone of the layers is a topmost layer, comprising the steps of:forming aplanarizing block mask, said planarizing block mask being a combinedweighted inverse spatial interpolation of each said pattern mask, saidplanarizing block mask being formed by ANDing the inverse of each ofsaid pattern masks with an associated layer template mask to formweighted inverse masks and overlaying said weighted inverse masks;forming a planarizing block layer on top of said topmost layer usingsaid planarizing block mask; forming an unpatterned planarizing filmlayer on top of said planarizing block layer; and etching saidunpatterned planarizing film layer, said planarizing block layer, andsaid topmost layer to cause planarization of said topmost layer.
 2. Themethod of claim 1 wherein said step of forming a planarizing block maskcomprises the steps of:creating a global template mask comprising a gridof similarly shaped units wherein each said unit has been subdividedinto a plurality of subunits, wherein each unit has at least one subunitassociated with each patterned layer and wherein each subunit isassociated with only one patterned layer; creating layer template maskassociated with each said patterned layer, said layer template mask fora specific patterned layer comprising a series of boolean valuesassociated with each said subunit of said global template mask whereinall boolean values in a layer template mask have a value of false exceptfor boolean values associated with those subunits that were associatedwith said specific patterned layer when creating said global templatemask; creating said weighted inverse masks, said weighted inverse maskscreated for a particular patterned layer by taking the logical `and`between the inverse of said pattern mask and said layer template maskassociated with said particular patterned layer; and summing saidweighted inverse masks to form said planarizing block mask.
 3. Themethod of claim 1 wherein said step of forming a planarizing block maskcomprises the steps of:creating a global template mask comprising a gridof similarly shaped units wherein each said unit has been subdividedinto a plurality of subunits, wherein each unit has at least one subunitassociated with each patterned layer and wherein each subunit isassociated with only one patterned layer and wherein said similarlyshaped units are rectangles; creating a layer template mask associatedwith each said patterned layer, said layer template mask for a specificpatterned layer comprising a series of boolean values associated witheach said subunit of said global template mask wherein all booleanvalues in a layer template mask have a value of false except for booleanvalues associated with those subunits that were associated with saidspecific patterned layer when creating said global template mask;creating said weighted inverse mask, said weighted inverse mask createdfor a particular patterned layer by taking the logical `and` between theinverse of said pattern mask and said layer template mask associatedwith said particular patterned layer; and summing said weighted inversemasks to form said planarizing block mask.
 4. The method of claim 1wherein said step of forming a planarizing block mask comprises thesteps of:creating a global template mask comprising a grid of similarlyshaped units wherein each said unit has been subdivided into a pluralityof subunits, wherein each unit has at least one subunit associated witheach patterned layer and wherein each subunit is associated with onlyone patterned layer and wherein said subunits have equal area; creatinga layer template mask associated with each said patterned layer, saidlayer template mask for a specific patterned layer comprising a seriesof boolean values associated with each said subunit of said globaltemplate mask wherein all boolean values in a layer template mask have avalue of false except for boolean values associated with those subunitsthat were associated with said specific patterned layer when creatingsaid global template mask; creating said weighted inverse mask, saidweighted inverse mask created for a particular patterned layer by takingthe logical `and` between the inverse of said pattern mask and saidlayer template mask associated with said particular patterned layer; andsumming said weighted inverse masks to form said planarizing block mask.5. The method of claim 1 wherein said step of forming a planarizingblock mask comprises the steps of:creating a global template maskcomprising a grid of similarly shaped units wherein each said unit hasbeen subdivided into a plurality of subunits, wherein each unit has atleast one subunit associated with each patterned layer and wherein eachsubunit is associated with only one patterned layer wherein saidsubunits have an area proportional to the area of said unit such thatthe ratio of the area of a particular subunit to the area of said unitis substantially equal to the ratio of the thickness of the patternedlayer with which said particular subunit is associated to the sum of thethicknesses of said plurality of patterned layers; creating a layertemplate mask associated with each said patterned layer, said layertemplate mask for a specific patterned layer comprising a series ofboolean values associated with each said subunit of said global templatemask wherein all boolean values in a layer template mask have a value offalse except for boolean values associated with those subunits that wereassociated with said specific patterned layer when creating said globaltemplate mask; creating said weighted inverse mask, said weightedinverse mask created for a particular patterned layer by taking thelogical `and` between the inverse of said pattern mask and said layertemplate mask associated with said particular patterned layer; andsumming said weighted inverse masks to form said planarizing block mask.6. The method of claim 1 wherein said step of forming a planarizingblock mask comprises the steps of:creating a global template maskcomprising a grid of similarly shaped units wherein each said unit hasbeen subdivided into a plurality of subunits, wherein each unit has atleast one subunit associated with each patterned layer and wherein eachsubunit is associated with only one patterned layer; creating a layertemplate mask associated with each said patterned layer, said layertemplate mask for a specific patterned layer comprising a series ofboolean values associated with each said subunit of said global templatemask wherein all boolean values in a layer template mask have a value offalse except for boolean values associated with those subunits that wereassociated with said specific patterned layer when creating said globaltemplate mask; creating said weighted inverse mask, said weightedinverse mask created for a particular patterned layer by taking thelogical `and` between the inverse of said pattern mask and said layertemplate mask associated with said particular patterned layer; summingsaid weighted inverse masks to form a planarizing block mask; andwherein step of taking the inverse of said pattern masks furthercomprises the steps of: enlarging positive areas on each of saidpatterned masks to form enlarged masks; and taking the inverse of saidenlarged masks to form inverse masks.
 7. A method for performing globalplanarization of the top layer of a structure having multiple patternedlayers, during fabrication of an integrated circuit having a pluralityof patterned layers interleaved with a plurality of unpatterned layerswherein each of said patterned layers is associated with a pattern maskand wherein one of the layers is a topmost layer, comprising the stepsof;creating a weighted spatial interpolation of each of said patternmasks; taking the inverse of each of said weighted spatialinterpolations to form inverse interpolation masks; forming aplanarizing block mask by multiplying said inverse interpolation masks;forming a planarizing block layer on top of said topmost layer usingsaid planarizing block mask; forming an unpatterned planarizing filmlayer on top of said planarizing block layer; and etching saidunpatterned planarizing film layer, said planarizing block layer, andsaid topmost layer to cause planarization of said topmost layer.
 8. Themethod of claim 7 wherein said step of creating a weighted spatialinterpolation of each of said pattern masks comprises the stepsof:creating a global template mask comprising a grid of similarly shapedunits, wherein each said unit has been subdivided into a plurality ofsubunits, wherein each unit has at least one subunit associated witheach patterned layer, and wherein each subunit is associated with onlyone patterned layer; creating a layer template mask associated with eachsaid patterned layer, said layer template mask for a specific patternedlayer comprising a series of boolean values associated with each saidsubunit of said global template mask wherein all boolean values in alayer template mask have a value of false except for boolean valuesassociated with those subunits that were associated with said specificpatterned layer when creating said global template mask; and creating aweighted spatial interpolation of each said pattern mask, said weightedspatial interpolation created for a particular patterned layer by takingthe logical `and` between the pattern mask and the layer template maskassociated with said particular patterned layer.
 9. The method of claim7 wherein said step of creating a weighted spatial interpolation of eachof said pattern masks comprises the steps of:creating a global templatemask comprising a grid of similarly shaped units, wherein each said unithas been subdivided into a plurality of subunits, wherein each unit hasat least one subunit associated with each patterned layer, and whereineach subunit is associated with only one patterned layer wherein saidsimilarly shaped units are rectangles; creating a layer template maskassociated with each said patterned layer, said layer template mask fora specific patterned layer comprising a series of boolean valuesassociated with each said subunit of said global template mask whereinall boolean values in a layer template mask have a value of false exceptfor boolean values associated with those subunits that were associatedwith said specific patterned layer when creating said global templatemask; and creating a weighted spatial interpolation of each said patternmask, said weighted spatial interpolation created for a particularpatterned layer by taking the logical `and` between the pattern mask andthe layer template mask associated with said particular patterned layer.10. The method of claim 7 wherein said step of creating a weightedspatial interpolation of each of said pattern masks comprises the stepsof:creating a global template mask comprising a grid of similarly shapedunits, wherein each said unit has been subdivided into a plurality ofsubunits, wherein each unit has at least one subunit associated witheach patterned layer, and wherein each subunit is associated with onlyone patterned layer wherein said subunits have equal area; creating alayer template mask associated with each said patterned layer, saidlayer template mask for a specific patterned layer comprising a seriesof boolean values associated with each said subunit of said globaltemplate mask wherein all boolean values in a layer template mask have avalue of false except for boolean values associated with those subunitsthat were associated with said specific patterned layer when creatingsaid global template mask; and creating a weighted spatial interpolationof each said pattern mask, said weighted spatial interpolation createdfor a particular patterned layer by taking the logical `and` between thepattern mask and the layer template mask associated with said particularpatterned layer.
 11. The method of claim 7 wherein said step of creatinga weighted spatial interpolation of each of said pattern masks comprisesthe steps of:creating a global template mask comprising a grid ofsimilarly shaped units, wherein each said unit has been subdivided intoa plurality of subunits, wherein each unit has at least one subunitassociated with each patterned layer, and wherein each subunit isassociated with only one patterned layer and wherein said subunits havean area proportional to the area of said unit such that the ratio of thearea of a particular subunit to the area of said unit is approximatelyequal to the ratio of the thickness of the patterned layer with whichsaid particular subunit is associated to the sum of the thicknesses ofsaid plurality of patterned layers; creating a layer template maskassociated with each said patterned layer, said layer template mask fora specific patterned layer comprising a series of boolean valuesassociated with each said subunit of said global template mask whereinall boolean values in a layer template mask have a value of false exceptfor boolean values associated with those subunits that were associatedwith said specific patterned layer when creating said global templatemask; and creating a weighted spatial interpolation of each said patternmask, said weighted spatial interpolation created for a particularpatterned layer by taking the logical `and` between the pattern mask andthe layer template mask associated with said particular patterned layer.12. A method for performing global planarization of the top layer of astructure having multiple patterned layers, during fabrication of anintegrated circuit having a plurality of patterned layers interleavedwith a plurality of unpatterned layers wherein each of said patternedlayers is associated with a pattern mask and wherein one of the layersis a topmost layer, comprising the steps of:combining said pattern masksto form a planarizing block mask said combining step further comprising,summing a weighted spatial interpolation of each said pattern mask toform an intermediate mask; taking the inverse of said intermediate maskto form said planarizing block mask; forming a planarizing block layeron top of said topmost layer using said planarizing block mask; formingan unpatterned planarizing film layer on top of said planarizing blocklayer; and etching said unpatterned planarizing film layer, saidplanarizing block layer, and said topmost layer to cause planarizationof said topmost layer.
 13. The method of claim 12 wherein the summingstep comprises the steps of:creating a global template mask comprising agrid of similarly shaped units wherein each said unit has beensubdivided into a plurality of subunits wherein each unit has at leastone subunit associated with each patterned layer and wherein eachsubunit is associated with one and only one patterned layer; creating alayer template mask associated with each said patterned layer, saidlayer template mask for a specific patterned layer consisting of aseries of boolean values associated with each said subunit of saidglobal template mask wherein all boolean values in a layer template maskhave a value of false except for said boolean values associated withsaid subunits that were associated with said specific patterned layerwhen creating said global template mask; creating a weighted spatialinterpolation of each said pattern mask, said weighted spatialinterpolation created for a particular patterned layer by taking thelogical `and` between the pattern mask and the layer template maskassociated with said particular patterned layer; and summing saidweighted spatial interpolations to form an intermediate mask.
 14. Themethod of claim 13 wherein said similarly shaped units are rectangles.15. The method of claim 13 wherein said subunits have equal area. 16.The method of claim 13 wherein said subunits have an area proportionalto the area of said unit such that the ratio of the area of a particularsubunit to the area of said unit is approximately equal to the ratio ofthe thickness of the patterned layer with which said particular subunitis associated to the sum of the thicknesses of said plurality ofpatterned layers.